The present invention, in some embodiments thereof, relates to a method of designing dual-mode logic circuits and, more particularly, but not exclusively, to a method of designing dual-mode logic circuits using electronic design automation tools.
Circuit design is a complex process which takes into account not only the desired logic functionality, but other factors such as physical behavior (e.g. sizing, capacitance . . . ), timing issues (e.g. desired operating frequency, propagation delays, and rise/fall times) and various other parameters. Electronic design automation (EDA) systems are software tools to assist in the design of electronic systems such as integrated circuits. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips.
The most advanced EDA tools utilize a standard design flow (SDF) designed for CMOS logic gates. The SDF typically perform the logic circuit design in the following steps:                1) A formal description of the required logic behavior is provided in a hardware description language (HDL).        2) Logic synthesis to translate the HDL description into a discrete netlist of logic-gates and synchronous cells (such as registers\Flip-Flops etc.). Typically the synthesizers work with a library of static logic (asynchronous) blocks and dynamic logic (synchronous) blocks. For the static blocks the library includes various parameters (such as timing, capacitance, leakage currents, etc. . . . ). For the dynamic blocks the library includes some similar parameters (such as capacitance, leakage currents and more . . . ) and some different parameters (such as setup and hold timing parameters). Typically the logic-gates are static and the dynamic cells have no logic and only exist for synchronization purposes.        3) Placement and routing, based on the netlist and other parameters such as gate sizing.        
CMOS designated EDA tools (e.g. Synopsis, Cadence . . . ) have been developed over many years and are extremely sophisticated. However these systems are sub-optimal for other types of logic families, such as Domino logic gates. Designing an EDA for special logic families is impractical due to the complexity of the design process and would be very costly. It is therefore desirable to adapt the design process for special logic families (e.g. Domino logic) to the standard tools available for CMOS circuit design.
Another consideration in circuit design (custom design or automated tools design) is the critical path. The performance of most digital circuits and systems is determined by the delay of critical paths (CP). Even though standard synthesis tools attempt to design logic blocks without CP (i.e. equalized path delay), the slack from the targeted clock frequency always exists and should be repaired by designers. Many methods to meet these slacks have been proposed. These methods include adaptive voltage scaling with a CP emulator circuit, multi oxide thickness driven threshold-voltages, multi-channel lengths for energy reduction in the non-CPs and performance boost in the CPs. Another proposed solution is to apply a body bias on a non-CP to improve energy consumption and increase performance of the CPs. While the aforementioned methods alleviate the critical path slack problem, in most cases they also result in a significant increase of energy consumption.
Additional background art includes:    [1] R. Puri, A. Bjorksten and T. E. Rosser, “Logic optimization by output phase assignment in dynamic logic synthesis,” in Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, pp. 2-7, 1997.    [2] R. Hossain, High performance ASIC design, Cambridge University Press, 2008.    [3] B. Chappell, X. Wang, P. Patra, P. Saxena, J. Vendrell, S. Gupta, S. Varadaraj an, W. Gomes, S. Hussain and H. Krishnamurthy, “A system-level solution to domino synthesis with 2 GHz application,” in Computer Design: VLSI in Computers and Processors, 2002. Proceedings 2002 IEEE International Conference on, pp. 164-171, 2002.    [4] J. M. Rabaey, A. P. Chandrakasan and B. Nikolic, Digital integrated circuits, Prentice-Hall, 1996.    [5] N. F. Goncalves and H. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” Solid-State Circuits, IEEE Journal Of, vol. 18, pp. 261-266, 1983.    [6] A. Strollo, E. Napoli and D. De Caro, “New clock-gating techniques for low-power flip-flops,” in Proceedings of the 2000 international symposium on Low power electronics and design, pp. 114-119, 2000.    [7] T. Christiansen and R. L. Schwartz, Learning Perl, O'Reilly and Associates, 1997.    [8] I. E. Sutherland, R. F. Sproull and D. F. Harris, Logical effort: designing fast CMOS circuits, Morgan Kaufmann, 1999.    [9] D. Harris and M. A. Horowitz, “Skew-tolerant domino circuits,” Solid-State Circuits, IEEE Journal Of, vol. 32, pp. 1702-1711, 1997.    [10] K. Keutzer, K. Kolwicz and M. Lega, “Impact of library size on the quality of automated synthesis,” in Proc. of ICCAD, pp. 120-123, 1987.    [11] K. Scott and K. Keutzer, “Improving cell libraries for synthesis,” in Custom Integrated Circuits Conference, 1994, Proceedings of the IEEE 1994, pp. 128-131, 1994.    [12] J. Noullet and A. Ferreira-Noullet, “Do We Need So Many Cells for Digital ASIC Synthesis?” ELECTRON TECHNOLOGY-WARSAW-, vol. 32, pp. 272-276, 1999.    [13] Y. Kukimoto, M. Berkelaar and K. Sakallah, “Static timing analysis,” Logic Synthesis and Verification, pp. 373-401, 2002.    [14] T. Sasao, Switching theory for logic synthesis, Kluwer Academic Publishers, 1999.    [15] J. J. Zasio, K. C. Choy and D. R. Parham, Static Timing Analysis of Semiconductor Digital Circuits, 1990.    [16] M. Elgebaly and M. Sachdev, “Efficient Adaptive Voltage Scaling System Through On-Chip Critical Path Emulation,” in Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on, pp. 375-380, 2004.    [17] H. L. A. Chen, E. K. W. Loo, J. B. Kuo and M. J. Syrzycki, “Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90 nm MTCMOS Technology,” in Electrical and Computer Engineering, 2007. CCECE 2007. Canadian Conference on, pp. 1671-1674, 2007.    [18] N. Sirisantana, L. Wei and K. Roy, “High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness,” in Computer Design, 2000. Proceedings. 2000 International Conference on, pp. 227-232, 2000.    [19] M. Meijer and J. P. de Gyvez, “Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 20, pp. 42-51, 2012.    [20] Xiaomei Liu and S. Mourad, “Performance of submicron CMOS devices and gates with substrate biasing,” in Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, pp. 9-12 vol. 4, 2000.    [21] Jan M. Rabaey, A. P. Chandrakasan and Borivoje Nikolic, Digital integrated circuits: a design perspective Upper Saddle River, N.J.: Pearson Education, 2003, pp. 761.    [22] N. F. Goncalves and H. De Man, “NORA: a racefree dynamic CMOS technique for pipelined logic structures,” Solid-State Circuits, IEEE Journal of, vol. 18, pp. 261-266, 1983.    [23] Jan M. Rabaey, A. P. Chandrakasan and Borivoje Nikolic, “Digital integrated circuits: a design perspective” Upper Saddle River, N.J.: Pearson Education, 2003, ch. 4, pp. 222.    [24] S. P. Mohanty, N. Ranganathan, E. Kougianos and P. Patra, Low-power high-level synthesis for nanoscale CMOS circuits, Springer, 2008.    [25] A. T. Tran and B. M. Baas, “Design of an energy-efficient 32-bit adder operating at subthreshold voltages in 45-nm CMOS,” in Communications and Electronics (ICCE), 2010 Third International Conference on, pp. 87-91, 2010.    [26] M. Lehman and N. Burla, “Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units,” Electronic Computers, IRE Transactions on, vol. EC-10, pp. 691-698, 1961.    [27] S. Majerski, “On determination of optimal distributions of carry skips in adders,” Electronic Computers, IEEE Transactions on, pp. 45-58, 1967.    [28] A. Guyot, B. Hochet and J. M. Muller, “A way to build efficient carry-skip adders,” Computers, IEEE Transactions on, vol. 100, pp. 1144-1152, 1987.    [28] V. G. Oklobdzij a and E. R. Barnes, “Some optimal schemes for ALU implementation in VLSI technology,” in Computer Arithmetic (ARITH), 1985 IEEE 7th Symposium on, pp. 2-8, 1985.